october 2009 ? 2009 fairchild semiconductor corporation www.fairchildsemi.com FIN224C ? rev. 1.0.9 serdes? FIN224C ? 24-bit low-power serializer/deserializer FIN224C 24-bit low-power serializer/deserializer features data & control bits 24 frequency 20mhz capability hvga interface microcontroller / rgb controller usage i86 & m68 dynamic current 17ma at 10mhz standby current 10a core voltage (v dda/s ) 2.5v to 3.3v i/o voltage (v ddp ) 1.65v to 3.6v esd 15kv (iec) package mlp-40 (6 x 6mm) ordering information FIN224Cmlx, mlp-40 related resources ? for samples and questions, please contact: interface@fairchildsemi.com . description the FIN224C serdes? is a low-power serializer/ deserializer ( serdes?) that can help minimize the cost and power of transferring wide signal paths. through the use of serialization, the num ber of signals transferred from one point to another can be significantly reduced. typical reduction is 5:1 for unidirectional paths. through the use of differential signaling, shielding and emi filters can also be minimized, further reducing the cost of serialization. the differential signaling is also important for providing a noise-insensitive signal that can withstand radio and electrical noise sources. major reduction in power consumption allows minimal impact on battery life in mobile applications. it is possible to use a single phase-locked loop (pll) for most applications, including bi-directional operation. applications ? slider, folder, and clamshell mobile handsets ? gsm and cdma phones typical application deserializer 24-bit deserializer + - + - serializer 24-bit serializer baseband + - + - 2 2 70-130 ohms built-in voltage translation main display simple interface internal termination deserializer 24-bit deserializer + - + - serializer 24-bit serializer baseband + - + - 2 2 70-130 ohms built-in voltage translation main display simple interface internal termination figure 1. mobile phone example
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FIN224C ? rev. 1.0.9 2 serdes? FIN224C ? 24-bit low-power serializer/deserializer pin configuration pin name description strobe lvcmos strobe signal for latching data into the serializer (on rising edge) ckref lvcmos clock input and pll reference ckp lvcmos word clock output dp[24:1] lvcmos data i/o /diro lvcmos control output inversion of diri s1, s2 lvcmos select pins, controls the mode of operation, see table 1 diri lvcmos control, selects serializer or deserializer mode 0 deserializer 1 serializer dso+ / dsi- dso- / dsi+ serial data i/o cksi+, cksi- serial clock input ckso+, ckso- serial clock output vddp power supply for parallel i/o and internal circuitry vdds power supply for serial i/o vdda power supply for core gnd ground pins note: 1. 0 = v il ; 1 = v ih . 13 14 15 16 17 39 38 36 35 34 33 gnd pad must be grounded dp[9] /diro ckso+ ckso- dso+ / dsi- dso- / dsi+ cksi- cksi+ dp[8] dp[7] dp[6] dp[5] dp[4] dp[3] dp[2] dp[1] dp[19] dp[20] dp[21] dp[22] dp[23] dp[24] 1 dp[10] 2 4 dp[11] dp[12] 3 vddp 5 ckp 6 dp[13] 7 dp[14] 8 12 dp[18] 11 dp[17] 40 26 27 25 29 24 18 23 28 30 37 dp[15] 9 dp[16] 10 s2 vdds 22 21 19 20 32 31 s1 vdda diri strobe ckref 13 14 15 16 17 39 38 36 35 34 33 gnd pad must be grounded dp[9] /diro ckso+ ckso- dso+ / dsi- dso- / dsi+ cksi- cksi+ dp[8] dp[7] dp[6] dp[5] dp[4] dp[3] dp[2] dp[1] dp[19] dp[20] dp[21] dp[22] dp[23] dp[24] 1 dp[10] 2 4 dp[11] dp[12] 3 vddp 5 ckp 6 dp[13] 7 dp[14] 8 12 dp[18] 11 dp[17] 40 26 27 25 29 24 18 23 28 30 37 dp[15] 9 dp[16] 10 s2 vdds 22 21 19 20 32 31 s1 vdda diri strobe ckref figure 2. mlp-40 pinout (through view)
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FIN224C ? rev. 1.0.9 3 serdes? FIN224C ? 24-bit low-power serializer/deserializer table 1. serializer / deserializer, operation, and reset modes diri s1 s2 mode of operation x 0 0 reset mode lvcmos outputs = high impedance lvcmos inputs = known state 1 0 1 serializer mode 0 1 0 deserializer mode application diagrams ckref strobe dp[18:1] dp[19] dp[20] dp[21] dp[24:22] s1 s2 diri /diro ckp ckso+ ckso- dso+/dsi- dso-/dsi+ cksi+ cksi- vddp vdds/a pclk dp[17:0] hsync vsync /cs reset baseband processor gnd cksi+ cksi- dso-/dsi+ dso+/dsi- ckso+ ckso- gnd main display 18-bit rgb pclk data[17:0] hsync vsync /cs reset vddp vdds/a serializer FIN224C deserializer FIN224C 1.8v 2.8v ckp dp[18:1] dp[19] dp[20] dp[21] dp[24:22] s1 s2 diri /diro ckref strobe 2.8v 2.8v ckref strobe dp[18:1] dp[19] dp[20] dp[21] dp[24:22] s1 s2 diri /diro ckp ckso+ ckso- dso+/dsi- dso-/dsi+ cksi+ cksi- vddp vdds/a pclk dp[17:0] hsync vsync /cs reset baseband processor gnd cksi+ cksi- dso-/dsi+ dso+/dsi- ckso+ ckso- gnd main display 18-bit rgb pclk data[17:0] hsync vsync /cs reset vddp vdds/a serializer FIN224C deserializer FIN224C 1.8v 2.8v ckp dp[18:1] dp[19] dp[20] dp[21] dp[24:22] s1 s2 diri /diro ckref strobe 2.8v 2.8v figure 3. 18-bit rgb interface block diagram
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FIN224C ? rev. 1.0.9 4 serdes? FIN224C ? 24-bit low-power serializer/deserializer ckref strobe dp[8:1] dp[16:9] dp[17] dp[18] dp dp[24: s1 s2 diri /diro ckp ckso+ ckso- dso+/dsi- dso-/dsi+ cksi+ cksi- vddp vdds/a /we dp[7:0] dp[15:8] a0 /cs0 /cs1 reset baseband processor gnd cksi+ cksi- dso-/dsi+ dso+/dsi- ckso+ ckso- gnd main display 16-bit controller /we data[7:0] data[15:8] a0 /cs0 vddp vdds/a serializer FIN224C deserializer FIN224C 1.8v 2.8v ckp dp[8:1] dp[16:9] dp dp[18] dp[19] dp[24:20] s1 s2 diri /diro ckref strobe 2.8v 2.8v main display 8-bit controller /we data[7:0] a0 /cs1 clock source ckref strobe dp[ dp dp dp[ dp[19] dp[24:20] s1 s2 diri /diro ckp ckso+ ckso- dso+/dsi- dso-/dsi+ cksi+ cksi- vddp vdds/a /we dp[7:0] dp[15:8] a0 /cs0 /cs1 reset baseband processor gnd cksi+ cksi- dso-/dsi+ dso+/dsi- ckso+ ckso- gnd main display 16-bit controller /we data[7:0] data[15:8] a0 /cs0 vddp vdds/a serializer FIN224C deserializer FIN224C 1.8v 2.8v ckp dp dp[: dp[17] dp dp dp: s1 s2 diri /diro ckref strobe 2.8v 2.8v main display 8-bit controller /we data[7:0] a0 /cs1 clock source figure 4. dual-display controller interface block diagram additional application information flex cabling: the serial i/o information is transmitted at a high serial rate. care must be taken implementing this serial i/o flex cable. the following best practices should be us ed when developing the flex cabling or flex pcb. ? keep all four differential serial wires the same length. ? do not allow noisy signals over or near differential serial wires. example: no cmos traces over differential serial wires. ? design goal of 70 to 130 differential characteristic impedance. ? do not place test points on differential serial wires. ? design differential serial wires a minimum of 2cm away from the antenna. ? visit fairchild?s website at http://www.fairchildsemi.com/pr oducts/interface/userdes.html , contact your sales representative, or contact fairchild directly at interface@fairchildsemi.com for applications notes or flex guidelines.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FIN224C ? rev. 1.0.9 5 serdes? FIN224C ? 24-bit low-power serializer/deserializer absolute maximum ratings stresses exceeding the absolute maximum ratings may damage t he device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating c onditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v dd supply voltage -0.5 +4.6 v all input/output voltage -0.5 +4.6 v t stg storage temperature range -65 +150 c t j maximum junction temperature +150 c t l lead temperature (soldering, 4 seconds) +260 c esd iec 61000 board level 15.0 kv human body model, jesd22-a114 all pins 2.5 serial i/0, /res, par/spi to gnd 8.0 recommended operating conditions the recommended operating conditions table defines the condi tions for actual device operation. recommended operating conditions are specified to ensure optim al performance to the datasheet specific ations. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. unit v dda , v dds (1) supply voltage 2.5 3.3 v v ddp supply voltage 1.65 3.60 v t a operating temperature -30 +70 c note : 1. v dda and v dds supplies must be hardwired together to the same power supply.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FIN224C ? rev. 1.0.9 6 serdes? FIN224C ? 24-bit low-power serializer/deserializer electrical specifications values valid for over supply voltage and operating temperature r anges unless otherwise specified. typical values are tested at t a = 25c and v dd = 2.775v. symbol parameter test conditions min. typ. max. unit dc parallel i/o characteristics v ih input high voltage 0.65 x v ddp v ddp v v il input low voltage gnd 0.35 x v ddp v v oh output high voltage i oh = -2.0ma v ddp = 3.30.30v 0.75 x v ddp v v ddp = 2.50.20v v ddp = 1.80.18v v ol output low voltage i oh = -2.0ma v ddp = 3.30.30v 0.25 x v ddp v v ddp = 2.50.20v v ddp = 1.80.18v i in input current -5 5 a dc serial characteristics i odh output high source current -1.75 ma i odl output low source current 0.95 ma i oz disabled output leakage current ckso, dso = 0v to v dds , s2 = s1 = 0v 1 5 a i iz disabled input leakage current ckso, dso = 0v to v dds , s2 = s1 = 0v 1 5 r trm cksi, ds internal receiver termination resistor 100 z serial transmission line impedance 70 100 130 power characteristics idda/s ser v dda , v dds serializer static current all dp and control inputs at 0v or no ckref, diri = 1 4.5 ma idda/s des v dda , v dds derializer static current all dp and control inputs at 0v or no ckref, diri = 0 5 ma idd ser dynamic serializer current idd ser = idda + idds + iddp ckref = strobe, diri = 1 10mhz 11 ma 20mhz 15 ma idd des dynamic deserializer current idd ser = idda + idds + iddp ckref = strobe, diri = 0 10mhz 7 ma 20mhz 10 ma idd_pd v dd power-down current idd_pd = idda + idds + iddp s1 = s2 = 0 all inputs at gnd or v dd 0.1 a ac serializer, diri = 1 specifications f max maximum ckref frequency 2 20 mhz f ref ckref frequency relative to strobe 1.1 x f strobe 20 mhz t cpwh ckref clock high time 0.2 0.5 t t cpwl ckref clock low time 0.2 0.5 t t clkt lvcmos input transition time 90 ns t spwh strobe pulse width high/low (tx4) / 26 (tx22) / 26 ns t stc dp[n] setup to strobe t stc t htc strobe dp[24:1] t stc t htc t stc t htc strobe dp[24:1] 2.5 ns t htc dp[n] hold to strobe 2.0 ns
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FIN224C ? rev. 1.0.9 7 serdes? FIN224C ? 24-bit low-power serializer/deserializer symbol parameter test conditions min. typ. max. unit t tplls0 phase lock loop stabilization time 200 s t tplld0 pll disable time loss of clock 30 s ac deserializer, diri = 0 specifications t skew_ds- cks allowed ds-cks input signal skew -150 150 ps t rcoh ckp out low time ckref = strobe, a = (1/f)/13 13a-3 13a+3 ns t rcoh ckp out high time 13a-3 13a+13 ns t pdv data valid to ckp low 8a-6 8a+1 ns t rolh output rise time (20% to 80%) 18 ns t rolh output fall time (20% to 80%) 18 ns ac enable and disable timing t plz(hz) deserializer disable time 25 ns t pzl(zh) deserializer enable time 2 s t plz(hz) serializer disable time 25 ns t pzl(zh) serializer enable time 65 ns notes: 2. skew is measured from either the rising or falling edge of ckso clock to the rising or falling edge of dso. signals are edge aligned. both outputs should have identical load condtions for this test to be valid. 3. if ckref is not equal to strobe for the serializer, the ckp signal does not maintain a 50% duty cycle. the low time of ckp remains 13 bit times.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FIN224C ? rev. 1.0.9 8 serdes? FIN224C ? 24-bit low-power serializer/deserializer physical dimensions notes: a. conforms to jedec registration mo-220, variation wjjd-2 with exception that this is a sawn version.. b. dimensions are in millimeters. c. dimensions and tolerances per asme y14.5m-1994. d. land pattern per ipc sm-782. e. width reduced to avoid solder bridging. f. dimensions are not inclusive of burrs, mold flash, or tie bar protrusions. g. drawing filename: mkt-mlp40arev3. 6.00 6.00 0.80 max 0.10 c seating plane 0.08 c 0.05 0.00 (0.20) c 0.15 c 0.15 c pin #1 ident 0.50 4.20 4.00 0.50 0.30 4.20 4.00 0.50 0.10 cab 0.05 c 0.18-0.30 a b 6.38min 0.20min 4.77min 4.37max 0.28 max 0.50typ (0.80) x4 x40 e (datum a) (datum b) pin #1 id figure 6. 40-lead, molded leadless package (mlp), quad, jedec mo-220, 6mm square package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner wit hout notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to verify or o btain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . for current tape and reel specifications, visit fairchild semiconductor?s online packaging area: http://www.fairchildsemi.com/packaging/mlp40a.html ordering information part number operating temperature range eco status package packing method FIN224Cmlx -30 to +70c green 40-lead, molded leadless package (mlp), quad, jedec mo-220, 6mm square tape & reel for fairchild?s definition of eco status, please visit: http://www.fairchildsemi.com/com pany/green/rohs_green.html .
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FIN224C ? rev. 1.0.9 9 serdes? FIN224C ? 24-bit low-power serializer/deserializer
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